The present invention relates to a system control method, control processing system, and control processing apparatus and, more particularly, to a system control method for a control processing system which has a plurality of control processing apparatuses mutually connected via a connection network and performs control in cooperation with the respective control processing apparatuses by causing the respective control processing apparatuses to issue transactions containing various instructions as needed, a control processing system, and a control processing apparatus.
In various information processing apparatuses, when various kinds of processing are to performed by control processing apparatuses such as CPUs (to be referred to as chips hereinafter), desired processes are distributed and executed in a plurality of chips, thereby realizing a multiprocessor system which improves processing performance.
In such a control processing system, the respective chips share hardware resources such as a memory and other peripheral circuits. Each chip incorporates a cache (cache memory) for temporarily holding data read out from the memory or data to be written in the memory in order to make efficient access to the memory. The consistency of data must therefore be maintained among the caches held by the respective chips and the memory.
The snoop scheme has been widely used as processing for maintaining such consistency. In this scheme, in order to maintain the consistency of data in the respective chips and the memory, the respective chips output instructions called snoop transactions.
In this case, the snoop transactions issued by the respective chips must be ordered, and the order must be shared among the respective chips. If the respective chips individually maintain the consistency of data without sharing the order of snoop transactions, old data may be overwritten on new data, resulting in data destruction.
FIG. 19 shows an example of a multiprocessor system based on the snoop scheme. In this multiprocessor system, a plurality of chips 100-1 to 100-n are coupled to each other via a bus 101. Clock signals are distributed from one clock generating circuit 102 to the respective chips 100-1 to 100-n. In this scheme, the snoop transactions issued by the respective chips are ordered by the single bus, and hence it is easy for all the chips to share the order.
In such a conventional control processing system, however, since a single bus is used as a connection network through which the respective chips exchange transactions, if a failure occurs in the bus, all the chips are affected by the failure. In addition, since clock signals are distributed from the same clock generating circuit to the respective chips, if a failure occurs in the clock generating circuit, all the chips are affected by the failure.